Estimation of Propagation Delay considering Short-Circuit Current for Static CMOS Gates

| We present formula of propagation delay for static CMOS logic gates considering short-circuit current and current owing through gate capacitance and using the n-th power law MOSFET model which considers velocity saturation e ects. The short circuit current is represented by a piece-wise linear function, which enables detailed analysis of the transient behavior of a CMOS inverter. We found that the error of our formulas for a CMOS inverter is less than 8% from circuit simulation in most cases of our experiments. We also applied these formulas to logic gates made up of series-parallel connected MOSFETs by replacing the series-connected MOSFETs with an equivalent MOSFET. The in uence of short-circuit power on delay, which is explicitly modeled in our formula, is numerically demonstrated such that the in uence becomes large with slow input transition and small output load capacitance. Keywords|short-circuit current, propagation delay.